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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50201-2E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (x8/x16) FLASH MEMORY & 2M (x8/x16) STATIC RAM
MB84VD2108X-85/MB84VD2109X-85
s FEATURES
* Power supply voltage of 2.7 to 3.6 V * High performance 85 ns maximum access time * Operating Temperature -25 to +85 C * Package 61-ball FBGA, 56-pin TSOP(I)
(Continued)
s PRODUCT LINE UP
Flash Memory Ordering Part No. VCCf, VCCs = 3.0 V -0.3 V
+0.6 V
SRAM
MB84VD2108X-85/MB84VD2109X-85 85 85 35 85 85 45
Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns)
s PACKAGES
61-ball plastic FBGA 56-pin plastic TSOP(I)
(BGA-61P-M02)
(FPT-56P-M04)
MB84VD2108X-85/MB84VD2109X-85
(Continued)
1. FLASH MEMORY
* Simultaneous Read/Write operations (dual bank) Miltiple devices available with different bank sizes Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program * Minimum 100,000 write/erase cycles * Sector erase architecture Eight 4 K words and thirty one 32 K words. Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture MB84VD2108X : Top sector MB84VD2109X : Bottom sector * Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. * Low VCCf write inhibit 2.5 V * Hidden ROM (Hi-ROM) region 64K byte of Hi-ROM, accessible through a new "Hi-ROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC input pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status (MB84VD2108X : SA37, SA38 MB84VD2109X : SA0, SA1) At VIH, allows removal of boot sector protection At VACC, program time will reduse by 40%. * Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device * Please refer to "MBM29DL16XTD/BD" data sheet in detailed function
2. SRAM
* Power dissipation Operating: 50 mA max. Standby: 7 A max. * Power down features using CE1s and CE2s * Data retention supply voltage : 1.5 V to 3.6 V * CE1s and CE2s Chip Select * Byte data control : LBs (DQ0 to DQ7) , UBs (DQ8 to DQ15) * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
MB84VD2108X-85/MB84VD2109X-85
s PIN ASSIGNMENTS
(Top View)
A
N.C.
N.C.
N.C.
N.C.
B
N.C.
A7
LBS
WP/ ACC
WE
A8
A11
C
A3
A6
UBS
RESET
CE2S
A19
A12
A15
D
A2
A5
A18
RY/BY
N.C.
A9
A13
N.C.
E
N.C.
A1
A4
A17
A10
A14
N.C.
N.C.
F
N.C.
A0
VSS
DQ1
DQ6
SA
A16
N.C.
G
CEf
OE
DQ9
DQ3
DQ4
DQ13
DQ15/ A-1
CIOf
H
CE1S
DQ0
DQ10
VCCf
VCCs
DQ12
DQ7
VSS
J
DQ8
DQ2
DQ11
CIOS
DQ5
DQ14
K
N.C. 1 2 3 4
N.C. 5
N.C. 6 7 8 9
N.C. 10
61-ball FBGA
3
MB84VD2108X-85/MB84VD2109X-85
(Top View)
N.C. A15 A14 A13 A12 A11 A10 A9 A8 A19 N.C. WE CE2s RESET WP/ACC RY/BY UBs LBs A18 A17 A7 A6 A5 A4 A3 A2 A1 N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 A16 CIOf VSS SA DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 CIOs VCCs VCCf DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE1s CEf A0
56-pin TSOP (I)
4
MB84VD2108X-85/MB84VD2109X-85
s PIN DESCRIPTION
Pin A0 to A16 A-1, A17 to A19 SA DQ0 to DQ15 CEf CE1s CE2s OE WE RY/BY UBs LBs CIOf CIOs RESET WP/ACC N.C. VSS VCCf VCCs Function Address Inputs (Common) Address Input (Flash) Address Input (SRAM) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Open Drain Output Upper Byte Control (SRAM) Lower Byte Control (SRAM) I/O Configuration (Flash) CIOf = VIH is Word mode (x16) , CIOf = VIL is Byte mode (x8) I/O Configuration (SRAM) CIOs = VIH is Word mode (x16) , CIOs = VIL is Byte mode (x8) Hardware Reset Pin/Sector Protection Unlock (Flash) Write Protect/Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (SRAM) Input/Output I I I I/O I I I I I O I I I I I I Power Power Power
5
MB84VD2108X-85/MB84VD2109X-85
s BLOCK DIAGRAM
VCCf A0 to A19 A0 to A19 A-1 WP/ACC RESET CEf CIOf VSS
RY/BY
16 M bit Flash Memory DQ0 to DQ15/A-1
DQ0 to DQ15/A-1 VCCs A0 to A16 DQ0 to DQ15/A-1 VSS
SA LBs UBs WE OE CE1s CE2s CIOs
2 M bit Static RAM
6
MB84VD2108X-85/MB84VD2109X-85
s DEVICE BUS OPERATIONS
Table 2.1 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Word mode; CIOs = VCCs)
Operation (Note1, 3) CEf CE1s CE2s SA OE WE (Note 6) LBs UBs DQ0 to DQ7 DQ8 to DQ15 RESET WP/ACC (Note 5)
Full Standby
H H
H X L H X H X H X L
X L H X L X L X L H
X H X H L H
X H X H H L
X X X X X X
X X H X X X L
X X H X X X L L H L L H X
HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z DOUT DIN DOUT HIGH-Z DOUT DIN HIGH-Z DIN X DOUT DIN DOUT DOUT HIGH-Z DIN DIN HIGH-Z X
H
X
Output Disable L Read from Flash (Note 2) Write to Flash L L
H
X
H H
X X
Read from SRAM
H
L
H
X
H L L
H
X
Write to SRAM Temporary Sector Group Unprotection (Note 4) Flash Hardware Reset Boot Block Sector Write Protection
H
L
H
X
L
X
H L
H
X
X
X H X X
X X L X
X
X
X
X
VID
X
X X
X X
X X
X X
X X
X X
HIGH-Z HIGH-Z X X
L X
X L
Legend : L = VIL, H = VIH, X = VIL or VIH, See "ELECTRICAL CHARACTERISTICS 1. DC Characteristics" for voltage levels. Notes : 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. 4. It is also used for the extended sector group protections. 5. WP/ACC = VIL ; protection of boot sectors. WP/ACC = VIH ; removal of boot sectors protection. WP/ACC = VACC (9 V) ; Program time will reduce by 40%. 6. SA ; Don't care or Open.
7
MB84VD2108X-85/MB84VD2109X-85
Table 2.2 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Byte mode; CIOs = VSS)
Operation (Note 1, 3) CEf CE1s CE2s OE WE SA LBs (Note 6) UBs (Note 6) DQ0 to DQ7 DQ8 to DQ15 RESET WP/ACC (Note 5)
Full Standby
H H
H X L H X H X H X L L
X L H X L X L X L H H
X H X H L H L X
X H X H H L H L
X X X X X X SA SA
X X X X X X X X
X X X X X X X X
HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z DOUT DIN DOUT DIN DOUT DIN HIGH-Z HIGH-Z
H
X
Output Disable L Read from Flash (Note 2) Write to Flash Read from SRAM Write to SRAM Temporary Sector Group Unprotection (Note 4) Flash Hardware Reset Boot Block Sector Write Protection L L H H
H
X
H H H H
X X X X
X
X
X
X
X
X
X
X
X
X
VID
X
X X
H X X
X L X
X X
X X
X X
X X
X X
HIGH-Z HIGH-Z X X
L X
X L
Legend : L = VIL, H = VIH, X = VIL or VIH. See "ELECTRICAL CHARACTERISTICS 1. DC Characteristics" for voltage levels. Notes : 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. 4. It is also used for the extended sector group protections. 5. WP/ACC = VIL ; protection of boot sectors. WP/ACC = VIH ; removal of boot sectors protection. WP/ACC = VACC (9 V) ; Program time will reduce by 40%. 6. LBS, UBS ; Don't care or Open.
8
MB84VD2108X-85/MB84VD2109X-85
Table 2.3 User Bus Operations (Flash = Byte mode; CIOf = VSS, SRAM = Byte mode; CIOs = VSS)
Operation (Note 1, 3) CEf CE1s CE2s DQ15/ OE WE SA A-1 LBs (Note 6) UBs (Note 6) DQ0 to DQ7 DQ8 to DQ14 RESET WP/ ACC (Note 5)
Full Standby
H H
H X L H X H
X L H X L X L X L H H
X X X A-1
X H X H
X H X H
X X X X
X X X X
X X X X
HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z
H
X
Output Disable L Read from Flash (Note 2) Write to Flash Read from SRAM Write to SRAM Temporary Sector Group Unprotection (Note 4) Flash Hardware Reset Boot Block Sector Write Protection
H
X
L
X H X L L
A-1
L
H
X
X
X
DOUT
X
H
X
L H H
A-1 X X
H L X
L H L
X SA SA
X X X
X X X
DIN DOUT DIN
X HIGH-Z HIGH-Z
H H H
X X X
X
X
X
X
X
X
X
X
X
X
X
VID
X
X
H X X
X L X
X
X
X
X
X
X
HIGH-Z HIGH-Z
L
X
X
X
X
X
X
X
X
X
X
X
L
Legend : L = VIL, H = VIH, X = VIL or VIH. See "ELECTRICAL CHARACTERISTICS 1. DC Characteristics" for voltage levels. Notes : 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. 4. It is also used for the extended sector group protections. 5. WP/ACC = VIL ; protection of boot sectors. WP/ACC = VIH ; removal of boot sectors protection. WP/ACC = VACC (9 V) ; Program time will reduce by 40%. 6. LBS, UBS ; Don't care or Open.
9
MB84VD2108X-85/MB84VD2109X-85
s FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
* Eight 4 K words, and thirty one 32 K words. * Individual-sector, multiple-sector, or bulk-erase capability.
Word Mode Byte Mode SA38 : 8 KB (4 KW) SA37 : 8 KB (4 KW) SA36 : 8 KB (4 KW) Bank 1 MB84VD21081 Bank 1 MB84VD21082 Bank 1 MB84VD21083 SA35 : 8 KB (4 KW) SA34 : 8 KB (4 KW) SA33 : 8 KB (4 KW) SA32 : 8 KB (4 KW) SA31 : 8 KB (4 KW) SA30 : 64 KB (32 KW) SA29 : 64 KB (32 KW) SA28 : 64 KB (32 KW) Bank 1 MB84VD21084 SA27 : 64 KB (32 KW) SA26 : 64 KB (32 KW) SA25 : 64 KB (32 KW) SA24 : 64 KB (32 KW) SA23 : 64 KB (32 KW) SA22 : 64 KB (32 KW) SA21 : 64 KB (32 KW) SA20 : 64 KB (32 KW) SA19 : 64 KB (32 KW) SA18 : 64 KB (32 KW) SA17 : 64 KB (32 KW) SA16 : 64 KB (32 KW) SA15 : 64 KB (32 KW) SA14 : 64 KB (32 KW) Bank 2 MB84VD21081 SA13 : 64 KB (32 KW) SA12 : 64 KB (32 KW) SA11 : 64 KB (32 KW) Bank 2 MB84VD21082 SA10 : 64 KB (32 KW) SA9 : 64 KB (32 KW) SA8 : 64 KB (32 KW) Bank 2 MB84VD21083 SA7 : 64 KB (32 KW) SA6 : 64 KB (32 KW) SA5 : 64 KB (32 KW) SA4 : 64 KB (32 KW) Bank 2 MB84VD21084 SA3 : 64 KB (32 KW) SA2 : 64 KB (32 KW) SA1 : 64 KB (32 KW) SA0 : 64 KB (32 KW) 0FFFFFH 0FF000H 0FE000H 0FD000H 0FC000H 0FB000H 0FA000H 0F9000H 0F8000H 0F0000H 0E8000H 0E0000H 0D8000H 0D0000H 0C8000H 0C0000H 0B8000H 0B0000H 0A8000H 0A0000H 098000H 090000H 088000H 080000H 078000H 070000H 068000H 060000H 058000H 050000H 048000H 040000H 038000H 030000H 028000H 020000H 018000H 010000H 008000H 000000H 1FFFFFH 1FE000H 1FC000H 1FA000H 1F8000H 1F6000H 1F4000H 1F2000H 1F0000H 1E0000H 1D0000H 1C0000H 1B0000H 1A0000H 190000H 180000H 170000H 160000H 150000H 140000H 130000H 120000H 110000H 100000H 0F0000H 0E0000H 0D0000H 0C0000H 0B0000H 0A0000H 090000H 080000H 070000H 060000H 050000H 040000H 030000H 020000H 010000H 000000H
MB84VD2108X Sector Architecture (Top Boot Block)
10
MB84VD2108X-85/MB84VD2109X-85
* Eight 4 K words, and thirty one 32 K words. * Individual-sector, multiple-sector, or bulk-erase capability.
Word Mode Byte Mode
SA38 : 64 KB (32 KW) SA37 : 64 KB (32 KW) SA36 : 64 KB (32 KW) SA35 : 64 KB (32 KW) Bank 2 MB84VD21094 Bank 2 MB84VD21093 Bank 2 MB84VD21092 Bank 2 MB84VD21091 SA34 : 64 KB (32 KW) SA33 : 64 KB (32 KW) SA32 : 64 KB (32 KW) SA31 : 64 KB (32 KW) SA30 : 64 KB (32 KW) SA29 : 64 KB (32 KW) SA28 : 64 KB (32 KW) SA27 : 64 KB (32 KW) SA26 : 64 KB (32 KW) SA25 : 64 KB (32 KW) SA24 : 64 KB (32 KW) SA23 : 64 KB (32 KW) SA22 : 64 KB (32 KW) SA21 : 64 KB (32 KW) SA20 : 64 KB (32 KW) SA19 : 64 KB (32 KW) SA18 : 64 KB (32 KW) SA17 : 64 KB (32 KW) SA16 : 64 KB (32 KW) SA15 : 64 KB (32 KW) SA14 : 64 KB (32 KW) SA13 : 64 KB (32 KW) SA12 : 64 KB (32 KW) Bank 1 MB84VD21094 Bank 1 MB84VD21093 SA11 : 64 KB (32 KW) SA10 : 64 KB (32 KW) SA9 : 64 KB (32 KW) SA8 : 64 KB (32 KW) SA7 : 8 KB (4 KW) Bank 1 MB84VD21092 Bank 1 MB84VD21091 SA6 : 8 KB (4 KW) SA5 : 8 KB (4 KW) SA4 : 8 KB (4 KW) SA3 : 8 KB (4 KW) SA2 : 8 KB (4 KW) SA1 : 8 KB (4 KW) SA0 : 8 KB (4 KW)
0FFFFFH 0F8000H 0F0000H 0E8000H 0E0000H 0D8000H 0D0000H 0C8000H 0C0000H 0B8000H 0B0000H 0A8000H 0A0000H 098000H 090000H 088000H 080000H 078000H 070000H 068000H 060000H 058000H 050000H 048000H 040000H 038000H 030000H 028000H 020000H 018000H 010000H 008000H 007000H 006000H 005000H 004000H 003000H 002000H 001000H 000000H
1FFFFFH 1F0000H 1E0000H 1D0000H 1C0000H 1B0000H 1A0000H 190000H 180000H 170000H 160000H 150000H 140000H 130000H 120000H 110000H 100000H 0F0000H 0E0000H 0D0000H 0C0000H 0B0000H 0A0000H 090000H 080000H 070000H 060000H 050000H 040000H 030000H 020000H 010000H 00E000H 00C000H 00A000H 008000H 006000H 004000H 002000H 000000H
MB84VD2109X Sector Architecture (Top Boot Block)
11
MB84VD2108X-85/MB84VD2109X-85
Table 3.1 Sector Address Tables (MB84VD21081) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Address Range (Byte mode) A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1
Address Range (Word mode)
000000H to 007FFFH 008000H to 00FFFFH 010000H to 017FFFH 018000H to 01FFFFH 020000H to 027FFFH 028000H to 02FFFFH 030000H to 037FFFH 038000H to 03FFFFH 040000H to 047FFFH 048000H to 04FFFFH 050000H to 057FFFH 058000H to 05FFFFH 060000H to 067FFFH 068000H to 06FFFFH 070000H to 077FFFH 078000H to 07FFFFH 080000H to 087FFFH 088000H to 08FFFFH 090000H to 097FFFH 098000H to 09FFFFH 0A0000H to 0A7FFFH 0A8000H to 0AFFFFH 0B0000H to 0B7FFFH 0B8000H to 0BFFFFH 0C0000H to 0C7FFFH 0C8000H to 0CFFFFH 0D0000H to 0D7FFFH 0D8000H to 0DFFFFH 0E0000H to 0E7FFFH 0E8000H to 0EFFFFH 0F0000H to 0F7FFFH 0F8000H to 0F8FFFH 0F9000H to 0F9FFFH 0FA000H to 0FAFFFH 0FB000H to 0FBFFFH 0FC000H to 0FCFFFH 0FD000H to 0FDFFFH 0FE000H to 0FEFFFH 0FF000H to 0FFFFFH
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1
A14
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1
A13
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1
A12
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 000000H to 00FFFFH 010000H to 01FFFFH 020000H to 02FFFFH 030000H to 03FFFFH 040000H to 04FFFFH 050000H to 05FFFFH 060000H to 06FFFFH 070000H to 07FFFFH 080000H to 08FFFFH 090000H to 09FFFFH 0A0000H to 0AFFFFH 0B0000H to 0BFFFFH 0C0000H to 0CFFFFH 0D0000H to 0DFFFFH 0E0000H to 0EFFFFH 0F0000H to 0FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1F1FFFH 1F2000H to 1F3FFFH 1F4000H to 1F5FFFH 1F6000H to 1F7FFFH 1F8000H to 1F9FFFH 1FA000H to 1FBFFFH 1FC000H to 1FDFFFH 1FE000H to 1FFFFFH
Bank 2
SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33
Bank 1
SA34 SA35 SA36 SA37 SA38
12
MB84VD2108X-85/MB84VD2109X-85
Table 3.2 Sector Address Tables (MB84VD21091) Sector Address Bank Sector A19
SA0 SA1 SA2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Address Range (WORD mode)
000000H to 000FFFH 001000H to 001FFFH 002000H to 002FFFH 003000H to 003FFFH 004000H to 004FFFH 005000H to 005FFFH 006000H to 006FFFH 007000H to 007FFFH 008000H to 00FFFFH 010000H to 017FFFH 018000H to 01FFFFH 020000H to 027FFFH 028000H to 02FFFFH 030000H to 037FFFH 038000H to 03FFFFH 040000H to 047FFFH 048000H to 04FFFFH 050000H to 057FFFH 058000H to 05FFFFH 060000H to 067FFFH 068000H to 06FFFFH 070000H to 077FFFH 078000H to 07FFFFH 080000H to 087FFFH 088000H to 08FFFFH 090000H to 097FFFH 098000H to 09FFFFH 0A0000H to 0A7FFFH 0A8000H to 0AFFFFH 0B0000H to 0B7FFFH 0B8000H to 0BFFFFH 0C0000H to 0C7FFFH 0C8000H to 0CFFFFH 0D0000H to 0D7FFFH 0D8000H to 0DFFFFH 0E0000H to 0E7FFFH 0E8000H to 0EFFFFH 0F0000H to 0F7FFFH 0F8000H to 0FFFFFH
A17
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A14
0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A13
0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A12
0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 000000H to 001FFFH 002000H to 003FFFH 004000H to 005FFFH 006000H to 007FFFH 008000H to 009FFFH 00A000H to 00BFFFH 00C000H to 00DFFFH 00E000H to 00FFFFH 010000H to 01FFFFH 020000H to 02FFFFH 030000H to 03FFFFH 040000H to 04FFFFH 050000H to 05FFFFH 060000H to 06FFFFH 070000H to 07FFFFH 080000H to 08FFFFH 090000H to 09FFFFH 0A0000H to 0AFFFFH 0B0000H to 0BFFFFH 0C0000H to 0CFFFFH 0D0000H to 0DFFFFH 0E0000H to 0EFFFFH 0F0000H to 0FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1FFFFFH
Bank 1
SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22
Bank 2
SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
13
MB84VD2108X-85/MB84VD2109X-85
Table 3.3 Sector Address Tables (MB84VD21082) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1
Address Range (WORD mode)
000000H to 007FFFH 008000H to 00FFFFH 010000H to 017FFFH 018000H to 01FFFFH 020000H to 027FFFH 028000H to 02FFFFH 030000H to 037FFFH 038000H to 03FFFFH 040000H to 047FFFH 048000H to 04FFFFH 050000H to 057FFFH 058000H to 05FFFFH 060000H to 067FFFH 068000H to 06FFFFH 070000H to 077FFFH 078000H to 07FFFFH 080000H to 087FFFH 088000H to 08FFFFH 090000H to 097FFFH 098000H to 09FFFFH 0A0000H to 0A7FFFH 0A8000H to 0AFFFFH 0B0000H to 0B7FFFH 0B8000H to 0BFFFFH 0C0000H to 0C7FFFH 0C8000H to 0CFFFFH 0D0000H to 0D7FFFH 0D8000H to 0DFFFFH 0E0000H to 0E7FFFH 0E8000H to 0EFFFFH 0F0000H to 0F7FFFH 0F8000H to 0F8FFFH 0F9000H to 0F9FFFH 0FA000H to 0FAFFFH 0FB000H to 0FBFFFH 0FC000H to 0FCFFFH 0FD000H to 0FDFFFH 0FE000H to 0FEFFFH 0FF000H to 0FFFFFH
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1
A14
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1
A13
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1
A12
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 000000H to 00FFFFH 010000H to 01FFFFH 020000H to 02FFFFH 030000H to 03FFFFH 040000H to 04FFFFH 050000H to 05FFFFH 060000H to 06FFFFH 070000H to 07FFFFH 080000H to 08FFFFH 090000H to 09FFFFH 0A0000H to 0AFFFFH 0B0000H to 0BFFFFH 0C0000H to 0CFFFFH 0D0000H to 0DFFFFH 0E0000H to 0EFFFFH 0F0000H to 0FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1F1FFFH 1F2000H to 1F3FFFH 1F4000H to 1F5FFFH 1F6000H to 1F7FFFH 1F8000H to 1F9FFFH 1FA000H to 1FBFFFH 1FC000H to 1FDFFFH 1FE000H to 1FFFFFH
Bank 2
SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32
Bank 1
SA33 SA34 SA35 SA36 SA37 SA38
14
MB84VD2108X-85/MB84VD2109X-85
Table 3.4 Sector Address Tables (MB84VD21092) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Address Range (WORD mode)
000000H to 000FFFH 001000H to 001FFFH 002000H to 002FFFH 003000H to 003FFFH 004000H to 004FFFH 005000H to 005FFFH 006000H to 006FFFH 007000H to 007FFFH 008000H to 00FFFFH 010000H to 017FFFH 018000H to 01FFFFH 020000H to 027FFFH 028000H to 02FFFFH 030000H to 037FFFH 038000H to 03FFFFH 040000H to 047FFFH 048000H to 04FFFFH 050000H to 057FFFH 058000H to 05FFFFH 060000H to 067FFFH 068000H to 06FFFFH 070000H to 077FFFH 078000H to 07FFFFH 080000H to 087FFFH 088000H to 08FFFFH 090000H to 097FFFH 098000H to 09FFFFH 0A0000H to 0A7FFFH 0A8000H to 0AFFFFH 0B0000H to 0B7FFFH 0B8000H to 0BFFFFH 0C0000H to 0C7FFFH 0C8000H to 0CFFFFH 0D0000H to 0D7FFFH 0D8000H to 0DFFFFH 0E0000H to 0E7FFFH 0E8000H to 0EFFFFH 0F0000H to 0F7FFFH 0F8000H to 0FFFFFH
A17
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A14
0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A13
0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A12
0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 000000H to 001FFFH 002000H to 003FFFH 004000H to 005FFFH 006000H to 007FFFH 008000H to 009FFFH 00A000H to 00BFFFH 00C000H to 00DFFFH 00E000H to 00FFFFH 010000H to 01FFFFH 020000H to 02FFFFH 030000H to 03FFFFH 040000H to 04FFFFH 050000H to 05FFFFH 060000H to 06FFFFH 070000H to 07FFFFH 080000H to 08FFFFH 090000H to 09FFFFH 0A0000H to 0AFFFFH 0B0000H to 0BFFFFH 0C0000H to 0CFFFFH 0D0000H to 0DFFFFH 0E0000H to 0EFFFFH 0F0000H to 0FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1FFFFFH
Bank 1
SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23
Bank 2
SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
15
MB84VD2108X-85/MB84VD2109X-85
Table 3.5 Sector Address Tables (MB84VD21083) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1
Address Range (WORD mode)
000000H to 007FFFH 008000H to 00FFFFH 010000H to 017FFFH 018000H to 01FFFFH 020000H to 027FFFH 028000H to 02FFFFH 030000H to 037FFFH 038000H to 03FFFFH 040000H to 047FFFH 048000H to 04FFFFH 050000H to 057FFFH 058000H to 05FFFFH 060000H to 067FFFH 068000H to 06FFFFH 070000H to 077FFFH 078000H to 07FFFFH 080000H to 087FFFH 088000H to 08FFFFH 090000H to 097FFFH 098000H to 09FFFFH 0A0000H to 0A7FFFH 0A8000H to 0AFFFFH 0B0000H to 0B7FFFH 0B8000H to 0BFFFFH 0C0000H to 0C7FFFH 0C8000H to 0CFFFFH 0D0000H to 0D7FFFH 0D8000H to 0DFFFFH 0E0000H to 0E7FFFH 0E8000H to 0EFFFFH 0F0000H to 0F7FFFH 0F8000H to 0F8FFFH 0F9000H to 0F9FFFH 0FA000H to 0FAFFFH 0FB000H to 0FBFFFH 0FC000H to 0FCFFFH 0FD000H to 0FDFFFH 0FE000H to 0FEFFFH 0FF000H to 0FFFFFH
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1
A14
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1
A13
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1
A12
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 000000H to 00FFFFH 010000H to 01FFFFH 020000H to 02FFFFH 030000H to 03FFFFH 040000H to 04FFFFH 050000H to 05FFFFH 060000H to 06FFFFH 070000H to 07FFFFH 080000H to 08FFFFH 090000H to 09FFFFH 0A0000H to 0AFFFFH 0B0000H to 0BFFFFH 0C0000H to 0CFFFFH 0D0000H to 0DFFFFH 0E0000H to 0EFFFFH 0F0000H to 0FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1F1FFFH 1F2000H to 1F3FFFH 1F4000H to 1F5FFFH 1F6000H to 1F7FFFH 1F8000H to 1F9FFFH 1FA000H to 1FBFFFH 1FC000H to 1FDFFFH 1FE000H to 1FFFFFH
Bank 2
SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30
Bank 1
SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
16
MB84VD2108X-85/MB84VD2109X-85
Table 3.6 Sector Address Tables (MB84VD21093) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 SA5 SA6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Address Range (WORD mode)
000000H to 000FFFH 001000H to 001FFFH 002000H to 002FFFH 003000H to 003FFFH 004000H to 004FFFH 005000H to 005FFFH 006000H to 006FFFH 007000H to 007FFFH 008000H to 00FFFFH 010000H to 017FFFH 018000H to 01FFFFH 020000H to 027FFFH 028000H to 02FFFFH 030000H to 037FFFH 038000H to 03FFFFH 040000H to 047FFFH 048000H to 04FFFFH 050000H to 057FFFH 058000H to 05FFFFH 060000H to 067FFFH 068000H to 06FFFFH 070000H to 077FFFH 078000H to 07FFFFH 080000H to 087FFFH 088000H to 08FFFFH 090000H to 097FFFH 098000H to 09FFFFH 0A0000H to 0A7FFFH 0A8000H to 0AFFFFH 0B0000H to 0B7FFFH 0B8000H to 0BFFFFH 0C0000H to 0C7FFFH 0C8000H to 0CFFFFH 0D0000H to 0D7FFFH 0D8000H to 0DFFFFH 0E0000H to 0E7FFFH 0E8000H to 0EFFFFH 0F0000H to 0F7FFFH 0F8000H to 0FFFFFH
A17
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A14
0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A13
0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A12
0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 000000H to 001FFFH 002000H to 003FFFH 004000H to 005FFFH 006000H to 007FFFH 008000H to 009FFFH 00A000H to 00BFFFH 00C000H to 00DFFFH 00E000H to 00FFFFH 010000H to 01FFFFH 020000H to 02FFFFH 030000H to 03FFFFH 040000H to 04FFFFH 050000H to 05FFFFH 060000H to 06FFFFH 070000H to 07FFFFH 080000H to 08FFFFH 090000H to 09FFFFH 0A0000H to 0AFFFFH 0B0000H to 0BFFFFH 0C0000H to 0CFFFFH 0D0000H to 0DFFFFH 0E0000H to 0EFFFFH 0F0000H to 0FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1FFFFFH
Bank 1
SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25
Bank 2
SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
17
MB84VD2108X-85/MB84VD2109X-85
Table 3.7 Sector Address Tables (MB84VD21084) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 SA5 SA6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1
Address Range (WORD mode)
000000H to 007FFFH 008000H to 00FFFFH 010000H to 017FFFH 018000H to 01FFFFH 020000H to 027FFFH 028000H to 02FFFFH 030000H to 037FFFH 038000H to 03FFFFH 040000H to 047FFFH 048000H to 04FFFFH 050000H to 057FFFH 058000H to 05FFFFH 060000H to 067FFFH 068000H to 06FFFFH 070000H to 077FFFH 078000H to 07FFFFH 080000H to 087FFFH 088000H to 08FFFFH 090000H to 097FFFH 098000H to 09FFFFH 0A0000H to 0A7FFFH 0A8000H to 0AFFFFH 0B0000H to 0B7FFFH 0B8000H to 0BFFFFH 0C0000H to 0C7FFFH 0C8000H to 0CFFFFH 0D0000H to 0D7FFFH 0D8000H to 0DFFFFH 0E0000H to 0E7FFFH 0E8000H to 0EFFFFH 0F0000H to 0F7FFFH 0F8000H to 0F8FFFH 0F9000H to 0F9FFFH 0FA000H to 0FAFFFH 0FB000H to 0FBFFFH 0FC000H to 0FCFFFH 0FD000H to 0FDFFFH 0FE000H to 0FEFFFH 0FF000H to 0FFFFFH
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1
A14
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1
A13
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1
A12
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 000000H to 00FFFFH 010000H to 01FFFFH 020000H to 02FFFFH 030000H to 03FFFFH 040000H to 04FFFFH 050000H to 05FFFFH 060000H to 06FFFFH 070000H to 07FFFFH 080000H to 08FFFFH 090000H to 09FFFFH 0A0000H to 0AFFFFH 0B0000H to 0BFFFFH 0C0000H to 0CFFFFH 0D0000H to 0DFFFFH 0E0000H to 0EFFFFH 0F0000H to 0FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1F1FFFH 1F2000H to 1F3FFFH 1F4000H to 1F5FFFH 1F6000H to 1F7FFFH 1F8000H to 1F9FFFH 1FA000H to 1FBFFFH 1FC000H to 1FDFFFH 1FE000H to 1FFFFFH
Bank 2
SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26
Bank 1
SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
18
MB84VD2108X-85/MB84VD2109X-85
Table 3.8 Sector Address Tables (MB84VD21094) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Address Range (WORD mode)
000000H to 000FFFH 001000H to 001FFFH 002000H to 002FFFH 003000H to 003FFFH 004000H to 004FFFH 005000H to 005FFFH 006000H to 006FFFH 007000H to 007FFFH 008000H to 00FFFFH 010000H to 017FFFH 018000H to 01FFFFH 020000H to 027FFFH 028000H to 02FFFFH 030000H to 037FFFH 038000H to 03FFFFH 040000H to 047FFFH 048000H to 04FFFFH 050000H to 057FFFH 058000H to 05FFFFH 060000H to 067FFFH 068000H to 06FFFFH 070000H to 077FFFH 078000H to 07FFFFH 080000H to 087FFFH 088000H to 08FFFFH 090000H to 097FFFH 098000H to 09FFFFH 0A0000H to 0A7FFFH 0A8000H to 0AFFFFH 0B0000H to 0B7FFFH 0B8000H to 0BFFFFH 0C0000H to 0C7FFFH 0C8000H to 0CFFFFH 0D0000H to 0D7FFFH 0D8000H to 0DFFFFH 0E0000H to 0E7FFFH 0E8000H to 0EFFFFH 0F0000H to 0F7FFFH 0F8000H to 0FFFFFH
A17
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A14
0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A13
0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A12
0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 000000H to 001FFFH 002000H to 003FFFH 004000H to 005FFFH 006000H to 007FFFH 008000H to 009FFFH 00A000H to 00BFFFH 00C000H to 00DFFFH 00E000H to 00FFFFH 010000H to 01FFFFH 020000H to 02FFFFH 030000H to 03FFFFH 040000H to 04FFFFH 050000H to 05FFFFH 060000H to 06FFFFH 070000H to 07FFFFH 080000H to 08FFFFH 090000H to 09FFFFH 0A0000H to 0AFFFFH 0B0000H to 0BFFFFH 0C0000H to 0CFFFFH 0D0000H to 0DFFFFH 0E0000H to 0EFFFFH 0F0000H to 0FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1FFFFFH
Bank 1
SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29
Bank 2
SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
19
MB84VD2108X-85/MB84VD2109X-85
Table 4.1 Sector Group Addresses (MB84VD2108X) (Top Boot Block) Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 A19 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 A16 0 0 1 1 X X X X X X 0 0 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 X X X X X X 0 1 0 1 1 1 1 1 1 1 1 A14 X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 A13 X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA28 to SA30 SA4 to SA7 SA8 to SA11 SA12 to SA15 SA16 to SA19 SA20 to SA23 SA24 to SA27 SA1 to SA3 Sectors SA0
20
MB84VD2108X-85/MB84VD2109X-85
Table 4.2 Sector Group Addresses (MB84VD2109X) (Bottom Boot Block) Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 A17 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 A16 0 0 0 0 0 0 0 0 0 1 1 X X X X X X 0 0 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X 0 1 0 1 A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X SA38 SA35 to SA37 SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA8 to SA10 Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7
21
MB84VD2108X-85/MB84VD2109X-85
Table 5 Flash Memory Autoselect Codes Type Manufacturer's Code MB84VD21081 MB84VD21091 MB84VD21082 MB84VD21092 Device Code MB84VD21083 MB84VD21093 MB84VD21084 MB84VD21094 Sector Group protect *1 : A-1 is for Byte mode. *2 : Output 01H at protected sector address and output 00H at unprotected sector address. Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word A12 to A19 X X X X X X X X X Sector Group Address A6 VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL A1 VIL VIL VIL VIL VIL VIL VIL VIL VIL VIH A0 VIL VIH VIH VIH VIH VIH VIH VIH VIH VIL A-1*1 VIL VIL X VIL X VIL X VIL X VIL X VIL X VIL X VIL X VIL Code (HEX) 04H 36H 2236H 39 2239H 2D 222DH 2E 222EH 28H 2228H 2BH 222BH 33H 2233H 35 2235H 01H*2
22
MB84VD2108X-85/MB84VD2109X-85
Table 6 Flash Memory Command Definitions Command Sequence
Read/Reset (Note 1) Read/Reset (Note 1) Word Byte Word Autoselect Byte Program Word Byte Word Byte Word Byte 4 3 AAAH 555H AAAH 555H AAAH 555H AAAH BA BA 555H AAAH AAH Bus First Bus Second Bus Write Write Cycle Write Cycle Cycles Req'd Addr. Data Addr. Data 1 3 XXXH F0H 555H AAAH 555H AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H PA 55H AAH 2AAH 555H 2AAH 55H 55H Third Bus Write Cycle Addr. 555H AAAH (BA) 555H (BA) AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH Fourth Bus Read/Write Cycle RA RD Fifth Bus Sixth Bus Write Cycle Write Cycle
Data Addr. Data Addr. Data Addr. Data F0H
90H

A0H
PA 555H AAAH 555H AAAH
PD
2AAH 555H 2AAH 555H
555H AAAH SA
Chip Erase
6
AAH
55H
80H
AAH
55H
10H
Sector Erase
6 1 1 3
AAH B0H 30H AAH
55H 55H
80H 20H
AAH
55H
30H
Sector Erase Suspend Sector Erase Resume Set to Fast Mode Fast Program (Note 2) Word Byte Word Byte
2
XXXH A0H
PD F0H (Note6)
Reset from Fast Word Mode Byte (Note 2) Extended Sector Group Protection (Note 3) Query (Note 4) Hi-ROM Entry Hi-ROM Program (Note 5) Hi-ROM Erase (Note 5) Word Byte Word Byte Word Byte Word Byte Word Byte Word
2
BA
90H XXXH

4
XXXH 60H
SPA
60H
SPA
40H
SPA
SD

1
55H AAH 555H AAAH 555H
98H
2AAH 555H 2AAH
555H AAAH 555H

3
AAH
55H
88H
4
AAAH 555H AAAH 555H
AAH
555H 2AAH 555H 2AAH
55H
AAAH 555H AAAH (HRBA) 555H (HRBA) AAAH
A0H
PA 555H AAAH
PD
2AAH 555H
6
AAH
55H
80H
AAH
55H
HRA
30H
Hi-ROM Exit (Note 5)
4 Byte AAAH
AAH 555H
55H
90H XXXH 00H

23
MB84VD2108X-85/MB84VD2109X-85
1 : Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. 2 : This command is valid while Fast Mode. 3 : This command is valid while RESET = VID. 4 : The valid Address is A0 to A6. 5 : This command is valid while Hi-ROM mode. 6 : The data "00H" is also acceptable. Address bits A12 to A19 = X = "H" or "L" for all address commands except for Program Address (PA) , Sector Address (SA) , and Bank Address (BA) . Bus operations are defined in Table 2 "User Bus Operations". RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank address (A15 to A19) SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0) . HRA = Address of the Hidden-ROM area. Word mode : 0F8000H to 0FFFFFH Byte mode : 1F0000H to 1FFFFFH MB84VD2109X (Bottom Boot Type) Word mode : 000000H to 007FFFH Byte mode : 000000H to 00FFFFH HRBA = Bank address of the Hidden-ROM area. MB84VD2108X (Top Boot Type) : A15 = A16 = A17 = A18 = A19 = A20 = 1 MB84VD2109X (Bottom Boot Type) : A15 = A16 = A17 = A18 = A19 = A20 = 0 RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. SD = Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotectedsector addresses. The system should generate the following address patterns; Word mode : 555H or 2AAH to addresses A0 to A10 Byte mode : AAAH or 555H to addresses A-1 and A0 to A10 MB84VD2108X (Top Boot Type)
24
MB84VD2108X-85/MB84VD2109X-85
s ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, RESET, WP/ACC (Note 1) VCCf/VCCs Supply (Note 1) A9 and OE (Note 2) RESET (Note 2) WP/ACC (Note 3) Symbol Tstg TA Rating Min. -55 -25 -0.3 -0.3 -0.3 -0.5 -0.5 Max. +125 +85 VCCf +0.4 VCCs +0.4 +4.0 +13.0 +13.0 +10.5 V V V V V Unit C C
VIN, VOUT VCCf, VCCs VIN VIN VIN
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Notes 1. Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf +0.4 V or VCCs+0.4 V. During voltage transitions, input or I/O pins may overshoot to VCCf+2.0 V or VCCs+2.0 V for periods of up to 20 ns. 2. Minimum DC input voltage on A9 and OE pin is -0.3 V. Minimum DC input voltage on RESET pin is -0.5 V. During voltage transitions, A9, OE, and RESET pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V. Maximum DC input voltage on A9, OE, and RESET pins is +13.0 V which may overshoot to 14.0 V for periods of up to 20 ns. 3. Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to 12.0 V for periods of up to 20 ns, when VCCf is applied.
s RECOMMENDED OPERATING RANGES
Parameter Ambient Temperature VCCf/VCCs Supply Voltages Symbol TA VCCf, VCCs Value Min. -25 +2.7 Max. +85 +3.6 Unit C V
Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 25
MB84VD2108X-85/MB84VD2109X-85
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter Symbol
Parameter Description Input Leakage Current Output Leakage Current RESET Inputs Leakage Current ACC Input Leakage Current Flash VCC Active Current (Read) (Note 1)
Test Conditions VIN = VSS to VCCf, VCCs VOUT = VSS to VCCf, VCCs VCCf = VCCf Max., VCCs = VCCs Max., RESET = 12.5 V VCCf = VCCf Max., VCCs = VCCs Max., WP/ACC = VACC Max. tCYCLE = 5 MHz Byte CEf = VIL, OE = VIH tCYCLE = 5 MHz Word tCYCLE = 1 MHz Byte tCYCLE = 1 MHz Word
Min. -1.0 -1.0 Byte Word Byte
Typ. 1
Max. +1.0 +1.0 35 20 13 15 7 7 35 48 50 48 50 35
Unit A A A mA mA mA mA
ILI ILO ILIT ILIA
ICC1f
ICC2f
Flash VCC Active Current CEf = VIL, OE = VIH (Program/Erase) (Note 2) Flash VCC Active Current (Read-While-Program) (Note 5) Flash VCC Active Current (Read-While-Erase) (Note 5) CEf = VIL, OE = VIH
ICC3f
mA
ICC4f
CEf = VIL, OE = VIH
Word
mA
ICC5f
Flash VCC Active Current CEf = VIL, OE = VIH (Erase-Suspend-Program) SRAM VCC Active Current VCCs = VCC Max., CE1s = VIL, CE2s = VIH tCYCLE = 10 MHz
mA
ICC1s

50 40 8 5
mA mA mA A A
ICC2s
SRAM VCC Active Current
tCYCLE = 10 MHz CE1s = 0.2 V, CE2s = VCCs - 0.2 V tCYCLE = 1 MHz
ISB1f
VCCf = VCC Max., CEf = VCCf 0.3 V Flash VCC Standby Current RESET = VCCf 0.3 V, WP/ACC = VCCf 0.3 V Flash VCC Standby Current (RESET) Flash VCC Current (Automatic Sleep Mode) (Note 3) VCCf = VCC Max., RESET = VSS 0.3 V, WP/ACC = VCCf 0.3 V VCCf = VCC Max., CEf = VSS 0.3 V RESET = VCCf 0.3 V, WP/ACC = VCCf 0.3 V VIN = VCCf 0.3 V or VSS 0.3 V
ISB2f
1
5
ISB3f

1
5
A A A
ISB1s ISB2s
SRAM VCC Standby Current CE1s VCCs - 0.2 V, CE2s VCCs - 0.2 V SRAM VCC Standby Current CE2s 0.2 V
0.2 0.2
7 7
(Continued)
26
MB84VD2108X-85/MB84VD2109X-85
(Continued)
Parameter Symbol
Parameter Description Input Low Level Input High Level Voltage for Sector Protection, and Temporary Sector Unprotection (RESET) (Note 4) Voltage for Program Acceleration (WP/ACC) (Note4) Output Low Voltage Level Output High Voltage Level Flash Low VCCf Lock-Out Voltage
Test Conditions
Min. -0.3 2.4
Typ.
Max. 0.5 VCC+0.3*
Unit V V
VIL VIH
VID
11.5
12.5
V
VACC
VCCf = VCCf Min., VCCs = VCCs Min., IOL = 1.0 mA VCCf = VCCf Min., VCCs = VCCs Min., IOH = -0.5 mA
8.5 2.4 2.3
9.0
9.5
V
VOL VOH VLKO
0.4 2.5
V V V
*: VCC indicates lower of VCCf or VCCs Notes : 1. The ICC current listed includes both the DC operating current and the frequency dependent component. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. Applicable for only VCCf applying. 5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
27
MB84VD2108X-85/MB84VD2109X-85
2. AC Characteristics
* CE Timing Parameter Symbols JEDEC Standard tCCR CE Recover Time Min. 0 ns Description Test Setup -85 Unit
* Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
CE1s
tCCR
tCCR
CE2s
28
MB84VD2108X-85/MB84VD2109X-85
* Read Only Operations Characteristics (Flash) Parameter Symbols Description JEDEC Standard tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCEf tOE tDF tDF tOH tREADY Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CEf or OE, Whichever Occurs First RESET Pin Low to Read Mode
Test Setup CEf = VIL OE = VIL OE = VIL
-85 (Note) Min. 85 0 Max. 85 85 35 30 30 20
Unit ns ns ns ns ns ns ns s
Note : Test Conditions-Output Load : 1 TTL gate and 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V to 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V
29
MB84VD2108X-85/MB84VD2109X-85
* Read Cycle (Flash)
tRC Addresses Stable
Addresses
tACC
CEf
tOE tDF
OE
tOEH
WE
tCEf HIGH-Z Output Valid HIGH-Z
DQ
tRC
Addresses
tRH tACC
Addresses Stable
CEf
tRP
tRH
tCEf
RESET
tOH HIGH-Z
DQ
Output Valid
30
MB84VD2108X-85/MB84VD2109X-85
* Erase/Program Operations (Flash) Parameter Symbols JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHEL tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 Standard tWC tAS tASO tAH tAHT tDS tDH tOES tOEH tCEPH tOEPH tGHEL tGHWL tWS tCS tWH tCH tWP tCP tWPH tCPH tWHWH1 tWHWH2 Write Cycle Time Address Setup Time (WE to Addr.) Address Setup Time to CEf Low During Toggle Bit Polling Address Hold Time (WE to Addr.) Address Hold Time from CEf or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and Data Polling
Description
-85 Min. 85 0 15 45 0 35 0 0 0 10 20 20 0 0 0 0 0 0 35 35 30 30 Typ. 8 16 1 Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s
CEf High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write (OE to CEf) Read Recover Time Before Write (OE to WE) WE Setup Time (CEf to WE) CEf Setup Time (WE to CEf) WE Hold Time (CEf to WE) CEf Hold Time (WE to CEf) Write Pulse Width CEf Pulse Width Write Pulse Width High CEf Pulse Width High Byte Programming Operation Word Programming Operation Sector Erase Operation (Note 1)
(Continued)
31
MB84VD2108X-85/MB84VD2109X-85
(Continued) Parameter Symbols
JEDEC Standard tVCS tVLHT tVIDR tVACCR tRB tRP tEOE tRH tBUSY tTOW tSPD VCCf Setup Time Voltage Transition Time (Note 2) Rise Time to VID (Note 2) Rise Time to VACC Recover Time from RY/BY RESET Pulse Width Delay Time from Embedded Output Enable RESET High Level Period Before Read Program/Erase Valid to RY/BY Delay Erase Time-out Time (Note 3) Erase Suspend Transition Time (Note 4)
Description
-85 Min. 50 4 500 500 0 500 200 50 Typ. Max. 85 90 20
Unit s s ns ns ns ns ns ns ns s s
Notes : 1.This does not include the preprogramming time. 2.This timing is for Sector Protection Operation. 3.The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will start. A time-out or "tTOW" from the rising edge of last CEf or WE whichever happens first will initiate the execution of the Sector Erase command (s) . 4.When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of "tSPD" to suspend the erase operation.
32
MB84VD2108X-85/MB84VD2109X-85
* Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling PA tAS tAH PA tRC
Addresses
555H tWC
CEf
tCS tCH tCEf
OE
tGHWL tWP tWPH tWHWH1 tOE
WE
tDS tDH tOH
DQ
A0H
PD
DQ7
DOUT
DOUT
Notes : 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the x16 mode. (The addresses differ from x8 mode.)
33
MB84VD2108X-85/MB84VD2109X-85
* Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Data Polling PA tAS tAH PA
Addresses
555H tWC
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CEf
tDS tDH
DQ
A0H
PD
DQ7
DOUT
Notes : 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the x16 mode. (The addresses differ from x8 mode.)
34
MB84VD2108X-85/MB84VD2109X-85
* AC Waveforms Chip/Sector Erase Operations (Flash)
Addresses
555H tWC
2AAH tAS tAH
555H
555H
2AAH
SA*
CEf
tCS tCH
OE
tGHWL tWP tWPH
WE
tDS tDH AAH 55H 80H AAH 55H 30H for Sector Erase 10H/ 30H
DQ
tVCS
VCCf
* : SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase. Note : These waveforms are for the x16 mode. (The addresses differ from x8 mode.)
35
MB84VD2108X-85/MB84VD2109X-85
* AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tOE
tDF
OE
tOEH
WE
tCEf
*
DQ7
Data In DQ7 DQ7 = Valid Data
High-Z
tWHWH1 or 2
DQ (DQ0 to DQ6)
Data In tBUSY
DQ0 to DQ6 = Output Flag
DQ0 to DQ6 Valid Data
High-Z
tEOE
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
36
MB84VD2108X-85/MB84VD2109X-85
* AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Addresses
tAHT tASO tAHT tAS
CEf
tCEPH
WE
tOEH
tOEPH tOEH
OE
tDH tOE Toggle Data tBUSY Toggle Data tCEf* Toggle Data Stop Toggling Output Valid
DQ6/DQ2
Data
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation) .
37
MB84VD2108X-85/MB84VD2109X-85
* Back-to-back Read/Write Timing Diagram (Flash)
Read tRC
Command tWC BA2 (555H) tAS tAH
Read tRC BA1 tACC tCEf
Command tWC BA2 (PA)
Read tRC BA1 tAS tAHT
Read tRC BA2 (PA)
Address
BA1
CEf
tOE tCEPH
OE
tGHWL tWP tOEH tDF
WE
tDS Valid Output Valid Input (A0H) tDH tDF Valid Output Valid Input (PD) Valid Output
DQ
Status
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address of Bank 1. BA2 : Address of Bank 2.
38
MB84VD2108X-85/MB84VD2109X-85
* RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
The rising edge of the last write pulse
WE
Entire programming or erase operations
RY/BY
tBUSY
* RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP tRB
RY/BY
tREADY
39
MB84VD2108X-85/MB84VD2109X-85
* Temporary Sector Unprotection (Flash)
VCCf
tVCS
tVIDR tVLHT
VID 3V RESET CEf
3V
WE
tVLHT tVLHT Program or Erase Command Sequence
RY/BY
Unprotection Period
40
MB84VD2108X-85/MB84VD2109X-85
* Extended Sector Protection (Flash)
VCCf
tVCS
RESET
tVIDR
tVLHT tWC tWC
Address
SGAx
SGAx
SGAy
A0
A1
A6
CEf
OE
TIME - OUT tWP
WE
Data
60H
60H
40H tOE
01H
60H
SGAx : Sector Group Address to be protected SGAy : Next Group Sector Address to be protected TIME-OUT : Time-Out window = 250 s (min.)
41
MB84VD2108X-85/MB84VD2109X-85
* Accelerated Program (Flash)
VCC tVCS VACC 3V WP/ACC
tVACCR tVLHT
3V
CE
WE tVLHT RY/BY Acceleration period Program or Erase Command Sequence tVLHT
42
MB84VD2108X-85/MB84VD2109X-85
* Read Cycle (SRAM) Parameter Symbol tRC tAA tCO1 tCO2 tOE tBA tCOE tOEE tBE tOD tODO tBD tOH Parameter Description Read Cycle Time Address Access Time Chip Enable (CE1s) Access Time Chip Enable (CE2s) Access Time Output Enable Access Time UBS, LBS to Output Valid Chip Enable (CE1s Low and CE2s High) to Output Active Output Enable Low to Output Active UBS, LBS Enable Low to Output Active Chip Enable (CE1s High or CE2s Low) to Output High-Z Output Enable High to Output High-Z UBS, LBS Output Enable to Output High-Z Output Data Hold Time Min. 85 5 0 0 10 Max. 85 85 85 45 85 35 35 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
43
MB84VD2108X-85/MB84VD2109X-85
* Read Cycle (Note) (SRAM)
tRC
Addresses
tAA tCO1 tOH
CE1s
tCOE tCO2 tOD
CE2s
tOD tOE
OE
tOEE tODO
LBs, UBs
tBA tBE tCOE tBD
DQ
VALID DATA OUT
Note : WE remains HIGH for the read cycle.
44
MB84VD2108X-85/MB84VD2109X-85
* Write Cycle (SRAM) Parameter Symbol tWC tWP tCW tAW tBW tAS tWR tODW tOEW tDS tDH Parameter Description Write Cycle Time Write Pulse Width Chip Enable to End of Write Address valid to End of Write UBS, LBS to End of Write Address Setup Time Write Recovery Time WE Low to Output High-Z WE High to Output Active Data Setup Time Data Hold Time Min. 85 55 70 70 55 0 0 0 35 0 Max. 35 Unit ns ns ns ns ns ns ns ns ns ns ns
45
MB84VD2108X-85/MB84VD2109X-85
* Write Cycle (Note 3) (WE control) (SRAM)
tWC
Addresses
tAS tWP tWR
WE
tAW tCW
CE1s
CE2s
tCW
tBW
LBs, UBs
tODW tOEW
DOUT
Note 1 tDS tDH
Note 2
DIN
Note 4
VALID DATA IN
Note 4
Notes : 1.If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 2.If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 3.If OE is HIGH during the write cycle, the outputs will remain at high impedance. 4.Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied.
46
MB84VD2108X-85/MB84VD2109X-85
* Write Cycle (Note 1) (CE1s control) (SRAM)
tWC
Addresses
tAS tWP tWR
WE
tAW tCW
CE1s
CE2s
tCW
tBW
LBs, UBs
tBE tCOE tODW
DOUT
tDS tDH
DIN
Note 2
VALID DATA IN
Notes : 1.If OE is HIGH during the write cycle, the outputs will remain at high impedance. 2.Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied.
47
MB84VD2108X-85/MB84VD2109X-85
* Write Cycle (Note 1) (CE2s Control) (SRAM)
tWC
Addresses
tAS tWP tWR
WE
tCW
CE1s
tAW
CE2s
tCW
tBW
LBs, UBs
tBE tCOE tODW
DOUT
tDS tDH
DIN
Note 2
VALID DATA IN
Notes : 1.If OE is HIGH during the write cycle, the outputs will remain at high impedance. 2.Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied.
48
MB84VD2108X-85/MB84VD2109X-85
* Write Cycle (Note 1) (LBS, UBS Control) (SRAM)
tWC
Addresses
tWP tWR
WE
tCW
CE1s
tCW
CE2s
tAW tAS tBW
LBs, UBs
tBE tCOE tODW
DOUT
tDS tDH
DIN
Note 2
VALID DATA IN
Notes : 1.If OE is HIGH during the write cycle, the outputs will remain at high impedance. 2.Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied.
49
MB84VD2108X-85/MB84VD2109X-85
s ERASE AND PROGRAMMING PERFORMANCE (Flash)
Parameter Sector Erase Time Byte Programming Time Word Programming Time Chip Programming Time Erase/Program Cycle Limits Min. 100,000 Typ. 1 8 16 Max. 10 300 360 50 Unit s s s s cycle Comment Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead
s DATA RETENTION CHARACTERISTICS (SRAM)
Parameter Symbol VDH IDDS2 tCDR tR Standby Current Chip Deselect to Data Retention Mode Time Recovery Time Parameter Description Data Retention Supply Voltage VDH = 3.0 V Min. 1.5 0 tRC Typ. 0.2 Max. 3.6 5* Unit V A ns ns
Note : tRC : Read cycle time * : 1 A Max. at TA 40 C * CE1s Controlled Data Retention Mode (Note 1)
VCCs 2.7 V
DATA RETENTION MODE
VIH VDH
CE1s
See Note 2
See Note 2
tCDR
VCCS -0.2 V
tR
GND
50
MB84VD2108X-85/MB84VD2109X-85
* CE2s Controlled Data Retention Mode (Note 3)
VCCs 2.7 V VDH VIH
DATA RETENTION MODE
CE2s
tCDR
tR
VIL
0.2 V
GND
Notes : 1.In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs-0.2 V or Vss to 0.2 V during data retention mode. Other input and input/output pins can be used between -0.3 V and Vccs + 0.3 V. 2.When CE1s is operating at the VIH min. level (2.2 V) , the standby current is given by ISB1s during the transition of VCCs from 3.6 to 2.2 V. 3.In CE2s controlled data retention mode, input and input/output pins can be used between -0.3 V and Vccs + 0.3 V.
s PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 CIN3 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Typ. 11 12 14 17 Max. 14 16 16 20 Unit pF pF pF pF
Note : Test conditions TA = 25 C, f = 1.0 MHz
s HANDLING OF PACKAGE
Please handle this package carefully since the sides of packages are right angle.
s CAUTION
1. The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not use autoselect and sector protect function by applying the high voltage (VID) to specific pins. 2. For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the sector using "Extended sector protect" command.
51
MB84VD2108X-85/MB84VD2109X-85
s ORDERING INFORMATION
MB84VD2108 X -85 -PBS
PACKAGE TYPE PBS = 61-ball FBGA PTS = 56-pin TSOP (I) SPEED OPTION See Product Selector Guide Device Revision
Bank Size 1 = 0.5 Mbit/ 15.5 Mbit 2 = 2 Mbit/ 14 Mbit 3 = 4 Mbit/ 12 Mbit 4 = 8 Mbit/ 8 Mbit
DEVICE NUMBER/DESCRIPTION 16 Mega-bit (2 M x 8-bit or 1 M x 16-bit) Dual Operation Flash Memory 3.0 V-only Read, Program, and Erase 2 Mega-bit (256 K x 8-bit or 128 K x 16-bit) SRAM BOOT CODE SECTOR ARCHITECTURE 84VD2108 = Top sector 84VD2109 = Bottom sector
52
MB84VD2108X-85/MB84VD2109X-85
s PACKAGE DIMENSIONS
61-ball plastic FBGA (BGA-61P-M02)
9.000.10(.354.004)SQ 1.25 -0.10 .049 -.004
+0.15 +.006
(Mounting height)
5.60(.220)REF 0.80(.031)
0.380.10 (Stand off) (.015.004)
10 9 8 0.80(.031) 5.60(.220) REF 7.20(.283) 7 6 5 4 3 2 1 HG INDEX-MARK AREA INDEX BALL 61-O0.45 -0.05 61-O0.18 -.002 0.10(.004)
+0.10 +.004
F
E
DC
B
A
0.08(.003)
M
C
1999 FUJITSU LIMITED B61002S-1C-1
Dimensions in mm (inches)
(Continued)
53
MB84VD2108X-85/MB84VD2109X-85
(Continued) 56-pin plastic TSOP(I) (FPT-56P-M04)
14.000.20(.551.008) 12.400.10(.488.004)
INDEX
0.40(.016) TYP 12.000.10 (.472.004)
0.180.035 (.007.001) "A"
0.10(.004)
M
Details of "A" part 0.25(.010)
0.145 .006
+0.05 -0.03 +.002 -.001
0.08(.003)
1.150.05 0.100.05 (.045.002) (.004.002) (Mounting height) (Stand off)
0~8
0.45/0.75 (.018/.030)
C
1998 FUJITSU LIMITED F56004S-1C-1
Dimensions in mm (inches)
54
MB84VD2108X-85/MB84VD2109X-85
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0007 (c) FUJITSU LIMITED Printed in Japan

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